1. Field of the Invention
The present invention relates to techniques for designing clock distribution networks for integrated circuit (IC) chips. More specifically, the present invention relates to a method and an apparatus for generating a clock-tree on an IC chip to facilitate reducing the effects of on-chip variation (OCV).
2. Related Art
Advances in semiconductor technology presently make it possible to integrate large-scale systems, including hundreds of millions of transistors, onto a single semiconductor chip. Integrating such large-scale systems onto a single semiconductor chip increases the speed at which such systems can operate, because signals between system components do not have to cross chip boundaries, and are not subject to lengthy chip-to-chip propagation delays.
The speed of a system on an integrated circuit (IC) chip is largely determined by system clock frequency. In a typical synchronous IC chip, a clock distribution network (referred to as a “clock-tree”) is used to distribute a clock signal from a common source to various circuit components. This clock signal is used to coordinate data transfers between circuit components. However, as increasing clock frequencies reduce the clock periods to fractions of a nanosecond, designing clock-trees is becoming increasingly more challenging. A direct result of the decreasing clock period is a shrinking “timing budget” between logically coupled clock sinks. This decreasing timing budget is requiring clock-trees to have minimal clock skew.
Many sources contribute to clock skew in a clock-tree. Among these sources, “variations” have become one of the more significant challenges in synchronous clock-tree design. These variations can include: manufacturing process variations, operational voltage variations, and ambient temperature variations. In particular, some of these variations occur within a chip boundary, and are hence referred to as “on-chip variations” (OCV). Due to the impact of OCV, the timing characteristics of instances of the same component may vary across the chip, thereby limiting the performance of the chip, and even threatening the functionality of the chip. Furthermore, OCV causes uncertainty in clock arrival times at circuit components. This uncertainty can cause clock skew and can thereby worsen the timing performance of the data paths between the clock sinks.
In order to reduce the effects of OCV, some systems insert shunt connections called “cross links” into a clock-tree structure in a post-processing step (see A. Rajaram, J. Hu and R. Mahapatra, “Reducing Clock Skew Variability via Cross Links,” IEEE Trans. Computer-Aided Design, Vol. 25, No. 6, pp. 1176-1182, June, 2006). These cross links can increase the amount of clock-path sharing between registers, thereby improving OCV-tolerance. However, this technique requires significantly more routing resources (wires) than would be needed by a typical clock-tree. Furthermore, the timing characteristics of the cross links are generally difficult to analyze. Another disadvantage of this technique is that additional wires also increase overall power consumption of the chip.
Other systems address the OCV issue by sequentially merging timing-critical pairs of registers based on a priority ordering (see D. Velenis, et al., “A clock tree topology extraction algorithm for improving the tolerance of clock distribution networks to delay uncertainty,” ISCAS 2001). However, this technique does not use any physical proximity information to guide clock-tree synthesis, and therefore suffers from problems such as unbalanced tree topology, larger wire length overhead, and higher power consumption.
Hence, what is needed is a method and an apparatus for creating an OCV-tolerant clock-tree without the problems described above.